1. Field of the Invention
The present invention relates to a parallel redundancy encoder, that can be used for transmitting parallel data in information and communication processing systems, of a simple configuration requiring no clock speed conversion, and to a channel-to-channel skew compensation apparatus for the data being transmitted in a plurality of channels.
2. Description of the Related Art
The present invention is based on Patent Applications Nos. Hei 10-032618, Hei 10-059542 and Hei 10-077783 filed in Japan, contents of which incorporated herein by reference.
Processing speeds of data processing devices such as central processor unit (CPU) in information and communication systems have shown yearly increase in recent years, brought about by improvements in operating speed of large scale integration (LSI) devices. Along with this trend, there has been an increasing demand for data transfer speeds between data processing devices. Also, to improve processing capability of such systems, progress has been made in the technology for operating a plurality of devices in parallel, and there has been increasing demand for improved performance of data transmission over a long distance.
Optical data transmission is capable of transmitting data at high speeds over long distances, and expectations are high for its use within a system for the purpose of information processing and data communication. Within such a system, data are processed as 8-bit or 16-bit parallel data, and therefore, an optical data transfer system must also be capable of providing parallel data transfer. Data transfer based on optical devices is often carried out by encoding the data to obtain stability in d.c. signal level of incoming data and to enable detection and correction of data errors.
Data transmission duration in parallel data transmission systems described above can vary from channel to channel, because of differences in the performance characteristics of each channel and operating characteristics of communication circuitries, resulting in a scatter in data arrival times of data transmitted through different channels. For this reason, differences in arrival times are generated in the receiver-side of such parallel data transmission systems. The differences in data arrival times in different transmission channels are referred to as channel-to-channel skew.
When the speed of data transmission is slow or the distance of transmission is short, channel-to-channel skew is negligibly small compared with a unit clock time of the parallel interconnection system, such that it does not present a serious problem. However, as the speed of data transmission increases as the unit clock time of the parallel interconnection system becomes shorter in high speed transmission systems, data can no longer be received normally at the receiver terminal due to the channel-to-channel skew effects. Also, because the scatter in data arrival times caused by differences in the performance characteristics of the channels are proportional to the transmission distance, so the longer the distance of parallel data transmission the larger the channel-to-channel skew effects, and normal data communication becomes difficult.
For this reason, to increase the speed and distance of transmission of parallel interconnection systems, it becomes important to compensate for the channel-to-channel skew. In particular, increased transmission speed and distance in parallel interconnection systems can be more readily attained by optical methods rather than electrical methods, and compensation for channel-to-channel skew becomes critical. Therefore, encoding is often used in parallel interconnection to enable such compensation for channel-to-channel skew effects.
Here, one of the encoding methods known to enable skew compensation is to insert mxe2x80x2 bits of redundant data for each m bits of transmission data train in each channel, which called frame bits. In this encoding method, m-bits of transmission data and mxe2x80x2 bits of frame bits are combined to constitute a frame of m+mxe2x80x2 bits. FIG. 20 illustrates an example of bit arrangement in such a frame.
An apparatus known widely for multiplexing data produced by parallel redundancy encoding is shown in FIG. 21. Encoder 75 performs parallel/serial conversion of m-bit parallel data and mxe2x80x2-bit redundant data output from a redundant data generator 76 to a serial data train in a p-s conversion section 77 at m+mxe2x80x2:1 clock rate. One apparatus of parallel redundancy encoder 70 is comprised by arranging several encoders 75 in parallel.
In contrast, FIG. 22 shows a functional block diagram of a parallel redundancy encoder that does not multiplex data for transmission. Encoder 75 inserts mxe2x80x2 bit of redundant data output from redundant data generator 79 for each m bits of data train input into a frame bit insertion section 78 at a bit speed of f0, and encodes the combined data by sending at a bit speed of (m+mxe2x80x2)/(m)xc3x97f0. One parallel redundancy encoder 70 is comprised by arranging several encoders 75 in parallel.
Other well known types of encoding method include xe2x80x9cmB1A codingxe2x80x9d which adds one auxiliary bit for each m bits of data. Variations of mB1A coding include a case of using the auxiliary bit as the parity bit, known as xe2x80x9cmB1P codingxe2x80x9d, and a case of using a coding bit for the preceding bit, known as xe2x80x9cmB1C codingxe2x80x9d. Also, in addition to those method that rely on inserting a special frame bit in frames in each channel, there are encoding methods that do not use frame bits, represented typically by xe2x80x9c8B10B codingxe2x80x9d.
Next, FIG. 23 shows an example of the conventional channel-to-channel skew compensation apparatus received in the receiver channels that detects and compensate for the skewing amount in data generated by such parallel redundancy encoder described above. In the channel-to-channel skew compensator, shown in FIG. 23, pre-selected one channel among the parallel interconnections is designated as the reference group train, i.e., the master channel. Master channel frame sync circuit 82 enters master channel input data into the master channel and outputs master channel frame signals (sync signals) to indicate the input data positions along the time axis.
In all channels other than in the master channel, each frame sync circuit 83 enters own input data into respective channels, and generates frame signals to indicate the input data positions along respective time axes. In all channels other than the master channel, own comparison circuit 84 is provided. Each comparison circuit 84 compares frame signals in own channel with master channel frame signals. In other words, comparison circuit 84 determines how far ahead or behind its own frame signal is compared with the corresponding master frame signal, and outputs advance/delay information as a skew signal.
Input data into the master channel are delayed by the master channel data delaying circuit 85 for a pre-determined time duration. All input data other than the master channel data are delayed by their own data delaying circuit 86. Each data delaying circuit 86 receives own skew signal, and adjusts the degree of skewing so as to match own frame position to the respective master frame position.
The location of master channel data delaying circuit 85, whether it is in front or back of the master channel frame sync circuit 82, does not affect the operating principle. Resulting from such series of adjustment steps, parallel data compensated for channel-to-channel skewing are generated.
However, in the conventional channel-to-channel skew compensation apparatus, should the degree of skewing is altered in the master channel, master signal timing is altered, i.e., reference positions of the master channel frame signals are altered. Therefore, in all the channels other than in the master channel, each comparison circuit 84 adjusts the degree of skewing produced by the respective data delaying circuits 86. When the signal delay amount is changed according to the adjustment in the master channel, positions (timing) of the data bit train of the skew-compensated data become instantaneously shifted with respect to the master frame positions, thereby creating errors in the transmitted data.
For example, in case the bit numbers for the reference time point for data in the channel-to-channel skew compensation apparatus change in a sequence such as 1,2,3,4,5, . . . , at the time the bit number of the reference time point is 2, when the amount of signal delay is updated and the position of the data is shifted one bit in the advancing direction, the data for the bit numbers 1,2,4,5, . . . appear in the data after compensation, which is to say that the bit number 3 disappears.
Additionally, in case the bit numbers for the reference time point for data in the channel-to-channel skew compensation apparatus change in a sequence such as 1,2,3,4,5, . . . , at the time the bit number of the reference time point is 3, when the amount of signal delay is updated and the position of the data is shifted one bit in the reversing direction, the data for the bit numbers 1,2,3,3,4,5, . . . appear in the data after compensation, which is to say that the bit number 3 is replicated.
Of course, when skewing is altered in the channels, unless the signal delay amount is updated, continuous errors would be generated in the skew-compensated data due to inappropriate actions in the channel-to-channel skew compensation apparatus, and therefore, updating of delay amount is absolutely essential. It should be noted that this type of error can be generated in all the channels excepting in the master channel.
Also, for designing a channel-to-channel skew compensation apparatus such as the one shown in FIG. 23, two extreme delay possibilities must be considered for the master channel: master channel may be the channel exhibiting either the maximum delay or the minimum delay.
For example, when deciding the bit numberxc3x97(natural number) to compensate for a possible amount of channel-to-channel skew, data delay in the master channel data delaying circuit 85 may be chosen to be (x+1) bits, then, in channels other than the master channel, it is necessary to select the maximum data delay in the data delay circuit 86 to be (2xc3x97x+1) bits.
Consequently, in the conventional channel-to-channel skew compensation apparatus for guaranteeing x-bits compensation for channel-to-channel skewing, a maximum delay of (2xc3x97x+1) bits is generated. Such a large amount of delay is detrimental to the development of high speed parallel data transmission system.
Another known type of skew control incorporates a synchronization guard circuit in the channel-to-channel skew compensation apparatus to prevent erroneous operation caused by noise and increase the reliability of frame synchronization. In such a system, a synchronization guard circuit is provided, and signal delay amount is updated in each channel when frame bits are detected contiguously over a certain number of frames at the same timing as inside the frame.
In such a channel-to-channel skew compensation apparatus, between the time of alteration in skewing and updating of signal delay amount by returning to frame synchronization state, there may be a delay in controlling the skew for an interval of up to ten times the frame length, for example, and during this delay interval, erroneous data will continue to be output as skew-compensated data. Such a problem can happen in various kinds of channel-to-channel skew compensation apparatuses equipped with a synchronization guard circuit to increase the reliability of frame synchronization.
In the parallel redundancy encoder such as the ones shown in FIGS. 21, 22, bit speed of input data is different than the bit speed of output data such that it is necessary to provide two types of clocks operating at different speeds. For this reason, it becomes necessary to provide a PLL circuit (phase-locked loop circuit: phase synchronizing loop circuit), however when a PLL circuit is included in an encoding device, it creates a problem that the circuit size becomes large. Also, PLL circuit must be adjusted to the speed of the drive clock, thus creating a problem that it cannot be operated at any desired clock speed. Furthermore, in the conventional parallel encoding method described above, there is a problem that clock speed conversion circuits become necessary in the receiver-side decoder for deleting redundant data from the transmitted data.
Therefore, one object of the present invention relates to a technique of encoding parallel data, and to provide a parallel redundancy encoding apparatus, of a relatively simple construction by eliminating the need for speed conversion circuits, that can respond flexibly to changes in bit speeds.
Another object is to provide a channel-to-channel skew compensation apparatus that can prevent changes in skewing amount generated in one problem transmission channel from affecting other problem-free transmission channels and to adjust the delay amount in the problem channel by using the skew compensation circuit.
Further object is to provide a channel-to-channel skew compensation apparatus that can prevent outputting erroneous data by shortening the time span between a state of frame synchronization loss and regaining of a state of frame synchronization to update the signal delay amount.
The object related to parallel redundancy encoding has been achieved in a parallel redundancy encoding apparatus to encode m channels of parallel data input in synchronization with clock signals, comprising: a redundancy generation section for generating mxe2x80x2 channels of redundant data; and a data switching section for accepting m+mxe2x80x2 channels of parallel input data, comprised by the mxe2x80x2 channels of redundant data added to the m channels of the parallel data, and outputting m+mxe2x80x2 channels of parallel data by switching data in each channel for every clock signal according to a pre-determined rule.
In the parallel redundancy encoding apparatus for encoding m channels of parallel data, it is preferable that the data switching section switches data according to a pre-determined pattern repeated at m+mxe2x80x2 clock cycles. It is also preferable that the data switching section switches data so as to output mxe2x80x2 clock pulse counts of redundant data between every channels operating at m+mxe2x80x2 clock cycles. Further, it is preferable that the data switching section switches data so as to produce a common serial pattern in all output channels, and that each serial pattern output is shifted by one bit in each channel with respect to a common reference time point. The apparatus may be operated such that the redundancy data generation section derives mxe2x80x2 channels of redundant data from a serial pattern of m channels of data according to a pre-determined rule.
According to the present parallel redundancy encoding apparatus to provide stability of direct current level in received signals, detection of channel-to-channel skewing and detection of data errors without the need of a speed conversion section. Because such speed conversion sections are not needed, encoding apparatus is simplified so that the apparatus presents many advantages including compact size, lower power consumption and overall cost. Also, because there is no need for speed conversion circuits which need to be adjusted to a particular operating speed, one parallel encoding apparatus can be operated at any desired clock speed, so that the need for providing a plurality of parallel encoding apparatuses to suit various operating speeds is eliminated. Further, because the encoding apparatus can be operated at any desired speed, it enables to realize an encoding apparatus that can be operated at various speeds to suit changes in the traffic density of transmission data. Such a parallel data encoding system can provide many advantages including lower power consumption.
The object related to channel-to-channel skew compensation has been achieved in a channel-to-channel skew compensation apparatus of the present invention comprising: an N number of frame synchronization circuits, provided for each transmission channel used, receiving parallel input data comprised by N parallel bits of not less than two bits located at identical bit-positions arranged on a common time axis, transmitted in parallel over N transmission channels, and generating frame signals to indicate positions of the parallel data on the common time axis for each operative transmission channel; a reference timing determination circuit for deciding a reference timing according to N pieces of frame signals output from the frame synchronization circuits; a skewing amount detection section for generating N pieces of skewing amount signals according to the reference timing determined by the reference timing determination circuit; and a timing compensation circuit provided in each transmission channel for adjusting output timing of the parallel data in individual transmission channels according to skewing amount signals generated by the skewing amount detection section.
Here, when a skew is not produced between the data of the contents of each transmission channel, the N frame signals generated on each of the above transmission channels have no relation to the contents of the data of each transmission channel, and all N frame signals are output from the synchronous frame circuit at the same time.
The skew compensation apparatus of such a construction has no special channel such as the master channel, but skewing amount is detected and compensated in each transmission channel individually. Reference timing required for detecting a skewing amount is determined according to N frame signals output from the frame sync circuit in each channel, thereby eliminating the need for special fixed channel so that the maximum delay amount required in timing compensation section is lessened compared with prior art systems. Therefore, the present system can operate more reliably.
For example, when the timing of the last signal of the N frame signals generated corresponding to each of the N transmission channels appearing at the reference time point is chosen as the reference timing, there are no frame signals after the reference timing, therefore, the timing compensation section only needs to delay the progress of the data by the amount of the clock pulse counts equal to reference timing. In other words, in the present channel-to-channel skew compensation apparatus, the maximum delay amount to guarantee skew compensation in all the channels is limited to (x+1) bits for x-bits frame length or the x-bits length of the bit holder. Also, the skewing amount detection section and timing compensation section are operating independently in individual channels so that skew problems in one channels does not affect other channels.
The reference timing determination circuit in the channel-to-channel skew compensation apparatus may include an N number of shift registers to store a plurality of N frame signals over given clock cycles, and a logic computation section to determine reference timing based on output signals from the shift registers.
For example, when a k-bit shift register is used for the above shift register, input signals can be stored in the shift register for a cyclic duration of k clock pulses. Therefore, when N frame signals in each transmission channel are held in the respective shift register for a plurality of clock cycles, a plurality of frame signals appearing at the common reference time point at different times on the common time axis can be monitored at the same timing. Thus, when channel-to-channel skewing is generated, the logic computation section needs to monitor the frame signals held in the shift register to check that all N signals have passed through within a given time. The reference timing is determined by the identify operation of the logic computation section.
Also, the skewing amount detection section in the channel-to-channel skew compensation apparatus may include a data holding section in each channel for holding signals output from the shift registers at a reference timing determined by the reference timing determination circuit.
That is, because the above construction allows N frame signals in each channel to be stored in the shift register during a plurality of clock cycles, a plurality of frame signals appearing at the common reference time point at different times on the common time axis can be monitored at the same timing. And, when N frame signals are held in the shift register, the data holding section latches the output signals from the shift register, and timing shift between the transmission channels, i.e. skewing, can be detected.
The logic computation section in the channel-to-channel skew compensation apparatus may include a start signal generation section for generating a start signal upon detecting that a frame signal is held in all N number of the shift registers in the reference timing determination circuit; and a counter section for counting a given count of clock pulses according to the start signal and repeatedly output the reference timing signals at a period identical to a frame period of the parallel data.
When data having a constant frame length is to be input, this construction allows the data to be input repeatedly to correspond with the frame length. By outputting reference timing signals at the same cycle as the frame period, skewing can be checked in individual data frames. The counter section checks one frame period.
The logic computation section in the channel-to-channel skew compensation apparatus may include a reset signal generation section for stopping operation of the counter section, when the counter section is outputting the reference signals, upon detecting that a frame signal is not held in any one of N shift registers in the reference timing determination circuit.
That is, when a reference timing is to be used after one frame period has passed since the frame period had been determined, it is necessary to consider fluctuation in skewing amount during the following one frame period. Particularly, if the first signal is advanced or the last signal is delayed in any of the N frame signals, there will be some channels for which skewing cannot be checked. Because the reset signal generation section generates a reset signal to stop the operation of the counter section, error generation can be suppressed.
The start signal generation section in the channel-to-channel skew compensation apparatus may include a mid-position identify section for generating a start signal, upon detecting that a frame signal is held in all N number of the shift registers in the reference timing determination circuit, by identifying a bit-position which appears first on the common time axis as a leading position of the N frame signals, and identifying another bit-position which appears last on the common time axis as a trailing position, so as to output a start signal when a mid-position frame between the leading position and the trailing position approaches a middle-bit position of a shift register in individual frame circuits.
That is, if the reference timing is selected when all N shift registers are holding a frame signal, if the last frame signal is further delayed due to fluctuation occurring in one frame period, there is high probability that some channels cannot be checked for skewing. Therefore, by adopting the above construction, the reference timing is selected when the mid-position of the overall range between the leading frame signal to the trailing frame signal coincides with the middle of the shift register. According to this approach, when the shift amount between the leading and trailing frame signals is sufficiently smaller than the number of bits in the shift register, even in a case of leading bit advancing or trailing bit delaying due to fluctuation caused within a frame period, probability is low that the position of these frames will be outside the holding capability of the shift register. Therefore, this approach minimizes generation of errors of this type.
The start signal generation section may include a multiple-position identify section for identifying a frame position on the common time axis that is shared by a maximum number of frame signals among N number of frame signals as a maximum position, so as to output the start signal when a frame signal on the maximum position approaches the middle-bit position of a shift register in individual frame circuits.
That is, variations in the required transmission time in individual channels are assumed to follow a statistical distribution pattern, and it may be considered that the probability is highest for the mid-position between the leading frame signal and the trailing frame signal to coincide with the middle-bit position of the shift register. Therefore, the above construction allows to select the reference timing to be the period between the mid-position of the frame coinciding with the middle-bit of the shift register. And, when the shift amount between the leading and trailing frame signals is sufficiently smaller than the number of bits in the shift register, even in a case of leading bit advancing or trailing bit delaying due to fluctuation caused within a frame period, probability is low that the position of these frames will be outside the holding capability of the shift register. Therefore, this approach minimizes generation of errors of this type.
The object to provide a channel-to-channel skew compensation apparatus that can shorten the time required to correct frame synchronization loss, caused by fluctuation in channel-to-channel skewing amount, to return to the frame synchronization state to enable to update the signal delay amount is achieved by providing skew compensation during decoding of error correction when the input parallel data have been encoded for error correction. It should be noted that xe2x80x9cparallel data encoded for error correctionxe2x80x9d means not only parallel data encoded by the present redundancy encoding apparatus but also those parallel data encoded by other methods.
That is, the above object is achieved in a channel-to-channel skew compensation apparatus, comprising: an error correction section receiving parallel data which have been error correction encoded for channel-to-channel positional shifts on the common time axis and decoding error corrections of the parallel data, and generating an error signal to indicate that there is or there is no error in each transmission channel; and a channel-to-channel skew compensation section for adjusting channel-to-channel positional shifts on the common time axis in the parallel input data.
The apparatus enables to detect bit errors in each channel during the decoding process of error correction encoded parallel data, and when the frequency of error detection is high, amount of skewing correction provided by the channel-to-channel skew compensation section is not appropriate, so that the amount of compensation is altered. On the other hand, if the frequency of error detection is low, the amount of compensation can be considered appropriate. In other words, controlling the channel-to-channel skew compensation section, according to the errors detected by the error correction section, enable channel-to-channel compensation of high reliability.
In addition, in the present channel-to-channel skew compensating apparatus, control is executed by error signals of high reliability output by the error correction section, so there is no need for checking the synchronization state over a large number of frames. That is, it is not necessary to check the synchronous state over a large number of frames by detecting frame synchronization or frame asynchronization based on error signals because the error signals output from the error correction section are output for every clock pulse, and when the channel-to-channel skewing amount fluctuates, the amount of skewing correction can be renewed very quickly by tracking the change in real-time.
The channel-to-channel skew compensation apparatus may be comprised by a frame position detection section in each transmission channel for detecting frame positions on a common time axis of the parallel input data; a channel-to-channel skew compensation section (20) for adjusting channel-to-channel positional shifts in the parallel data on the common time axis, based on frame positions in not less than two transmission channels on the common time axis detected by the frame position detection section; an error correction section receiving parallel data that are error correction encoded for channel-to-channel positional shifts on the common time axis, and decoding error corrections provided for the parallel data, and generating an error signal to indicate that there is or there is no error in each transmission channel; and an error control section for controlling a detection state of the frame position detection section according to error signals output by the error correction section.
In the above apparatus, frame position detection section detects frame positions in the parallel data in each transmission channel on the common time axis. The channel-to-channel skew compensation section adjusts positional shift of parallel data in different channels, according to frame positions in at least two transmission channels, detected by the frame position detection section, that are on the time axis. The error correction section receives parallel data corrected for positional shift on the time axis in different channels, and perform error correction decoding, and generates error signals, to indicate there is or there is no error, for each transmission channel. The error control section controls the detection state of each frame position detection section according to the error signals output from the error correction section.
When performing error correction decoding of the error correction encoded parallel data, it is possible to detect whether there is bit error in individual channels. When the frequency of error detection is high, amount of skewing correction provided by the channel-to-channel skew compensation section is not appropriate, so that the amount of compensation is altered. But, if the frequency of error detection is low, the amount of compensation can be considered appropriate.
By adopting the above construction, control is executed in real-time by error signals of high reliability output by error correction section to detect the detection state of the frame position detection section, so that there is no need for checking the synchronization state over a large number of frames. In other words, when the channel-to-channel skewing amount fluctuates, the amount of skewing correction can be renewed very quickly by tracking the changes in real-time.
In the above channel-to-channel skew compensation apparatus, a synchronization guard section may be provided in each transmission channel for delaying an adjustment of a positional shift, detected by the frame position detection section, to be applied by the channel-to-channel skew compensation section until specific conditions are fulfilled.
That is, transmitted signals are affected by noise, so that the reliability of such data as frame bit synchronization signals contained in parallel data is low. Therefore, by renewing the skewing amount according to simplistic synchronization signal only, such a correction process is susceptible to generation of large errors. Therefore, the above synchronization guard section delays applying the amount of skewing compensation detected by the frame position detection section to the channel-to-channel skew compensation section until certain conditions are established. This approach prevents identification of frame position caused by temporary disturbance caused by transient factors such as noise, thereby increasing the reliability of error control.
A frame loss detection section for the channel-to-channel skew compensation apparatus may be provided in each transmission channel for detecting a frequency of errors generated in each transmission channel, based on error signals output from the error correction section, and outputting a frame loss signal when the frequency of errors exceed a frame loss threshold value.
Accordingly, the synchronization guard section can identify from the frame loss signals that error generation frequency is higher than the threshold value. Therefore, it considers that frame loss has occurred, and can immediately transfer the operation to adjusting for frame synchronization.
Instead of the frame loss detection section, a frame synchronization detection section may be provided in each transmission channel for detecting a frequency of errors generated in each transmission channel, based on error signals output from the error correction section, and outputting a frame synchronization signal when the frequency of errors exceed a frame synchronization threshold value.
Accordingly, the synchronization guard section can identify from the frame synchronization signals that error generation frequency is less than the threshold value. Therefore, it considers that frame synchronization is appropriate, and can immediately transfer the operation to renewing the skewing amount.